1. Field of the Invention
The field of the invention relates to the field of data storage and in particular, to the storage and access of data in semiconductor memories.
2. Description of the Prior Art
With ever increasing demands to reduce both the size of devices and their power consumption, it is becoming increasingly challenging to design robust semiconductor memories such as SRAM. Each storage cell in an SRAM comprises a feedback loop for holding a data value. In order to write to the feedback loop and store a new value, the input data value must have a high enough voltage level to be able to switch the state stored by the feedback loop if required, while reading from the feedback loop should be performed without disturbing the values stored in any of the feedback loops.
As dimensions scale down the variations in device properties due to random dopant fluctuations, line edge roughness etc. increase drastically.
Thus, designing a robust SRAM where cells can written to across all operational voltage ranges turns out to be very difficult. Reducing the voltage at which the SRAM cells can be read and written to successfully is not easy and in particular as the voltage scales down it becomes increasingly difficult to write to the cells.
One proposed way of addressing the write problem is disclosed in “Low power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-IV Operation” by Iijima et al. Journal of Computers, vol 3, No 5 May 2008. FIG. 1 shows a circuit for boosting the word line voltage according to the technique disclosed in this article. In this circuit an active body-biasing controlled boost transistor generates a boost to the word line voltage thereby facilitating writes by capacitive coupling only when the word line is accessed. A drawback of this scheme is that there is a significant area overhead resulting from having one extra transistor per word line. Furthermore, since the signal controlling the PMOS pass gate is shorted to the back of the capacitive coupling transistor there is an inherent delay in turning off the PMOS pass gate. As a result of this delay some coupled charge will leak from the Vwl node through the partially turned on PMOS. This significantly reduces the efficiency of this scheme.
It would be desirable to be able to reduce write failures particularly during low voltage operation of a semiconductor memory.